Bioelectric Signal Compression Using Memristor-Based Architectures

Abstract

Compressive sensing (CS) and memristor-based hardware have become a paradigm shift for acquiring, compressing, and transmitting bioelectric signals from resources-limited implantable and wearable devices. This paper summarizes the theoretical underpinning, device physics, circuit architectures, and experimental performance evaluation of bioelectric signal compression using a memristor up to 2020. Memristors, the fourth fundamental circuit element predicted by Chua in 1971 and first realized physically by Strukov et al. in 2008, have resistance that varies with the history of the current applied to them that is particularly well suited for implementing the sparse projection operations at the heart of compressive sensing. Volatile nano-metal-oxide memristive encoders feature a power envelope of less than 100 nW, which allows for neuronal spike compression with ratios of more than 8× and percent root-mean-square difference (PRD) of 1.4%, while leading complementary metal-oxide semiconductor (CMOS) wireless body sensor implementations require 68.9 μW and can compress neuronal spikes with a ratio of less than 7× and a PRD of 2.1%. Fabricated architectures of crossbar arrays using metal-oxide resistive random-access memory (RRAM) cells enable in-memory matrix-vector multiplication, the computation challenge of CS reconstruction, with energy efficiencies of several orders of magnitude greater than that of traditional digital signal processors (DSPs). Additionally, on-chip adaptive learning is implemented with spike timing-dependent plasticity (STDP) using passive memristive circuits, which resulted in 96% in achieving neuronal waveform discrimination. The synthesis reveals key device design compromises of device variability, endurance and signal fidelity, and predicts near-term roadmaps for fully implantable neural interfaces under 1 μW into operation.